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ic-nqc 13-bit sin/d converter with signal calibration rev d1, page 1/ 29 features ? resolution of up to 8,192 angle steps per sine period ? binary and decimal resolution settings, e.g. 500, 512, 1000, 1024; programmable angle hysteresis ? count-safe vector follower principle, real-time system with 70 mhz sampling rate ? conversion time of just 250 ns including ampli?er settling ? direct sensor connection; selectable input gain ? input frequency of up to 250 khz ? signal conditioning for offset, amplitude and phase ? a/b quadrature signals of up to 3.75 mhz with adjustable minimum transition distance ? zero signal processing, adjustable in index position and width ? absolute angle output via fast serial interface (biss, ssi) ? permanent bidirectional memory access to parameters and oem data by biss c ? period counting with up to 24 bits ? error monitoring of frequency, amplitude and con?guration ? device setup from serial eeprom or using biss ? esd protection and ttl-/cmos-compatible outputs applications ? interpolator ic for angle resolution from sine/cosine sensor signals ? optical encoders ? mr sensor systems packages tssop20 block diagram copyright ? 2011 ic-haus http://www.ichaus.com p r e l i m i n a r y p r e l i m i n a r y
ic-nqc 13-bit sin/d converter with signal calibration rev d1, page 2/ 29 description ic-nqc is a monolithic a/d converter which, by ap- plying a count-safe vector follower principle, converts sine/cosine sensor signals with a selectable resolu- tion and hysteresis into angle position data. this absolute value is output via a bidirectional, synchronous-serial i/o interface in biss c protocol and trails a master clock rate of up to 10 mbit/s. alter- natively, this value can be output so that it is compat- ible with ssi in gray or binary code, with or without error bits. the device also supports double transmis- sion in ssi ring mode. signal periods are logged quickly by a 24-bit period counter that can supplement the output data with an upstream multiturn position value. at the same time any changes in angle are con- verted into incremental a quad b signals. here, the minimum transition distance can be stipulated and adapted to suit the system on hand (cable length, ex- ternal counter). a synchronized zero index z is gen- erated if enabled by pzero and nzero. the front-end ampli?ers are con?gured as instrumen- tation ampli?ers, permitting sensor bridges to be di- rectly connected without the need for external resis- tors. various programmable d/a converters are avail- able for the conditioning of sine/cosine sensor signals with regard to offset, amplitude ratio and phase er- rors (offset compensation by 8-bit dac, gain ratio by 5-bit dac, phase compensation by 6-bit dac). the front-end gain can be set in stages graded to suit all common complementary sensor signals from approximately 20 mvpp to 1.5 vpp and also non- complementary sensor signals from 40 mvpp to 3 vpp respectively. the device can be con?gured using two bidirectional interfaces, the eeprom interface from a serial eep- rom with i 2 c interface, or the i/o interface in biss c protocol. free storage space on the eeprom can be accessed via biss for the storage of additional data. after a low voltage reset, ic-nqc reads in the con?g- uration data including the check sum (crc) from the eeprom and repeats the process if a crc error is detected. p r e l i m i n a r y p r e l i m i n a r y
ic-nqc 13-bit sin/d converter with signal calibration rev d1, page 3/ 29 contents packages 4 absolute maximum ratings 5 thermal data 5 electrical characteristics 6 characteristics: diagrams . . . . . . . 8 operating requirements: i/o interface 9 parameter and register 10 signal conditioning 11 converter functions 12 maximum possible converter frequency 13 serial data output . . . . . . . . . . . . . . . 13 incremental output to a, b and z . . . . . . . 14 incremental signals 15 signal monitoring and error messages 17 test functions 18 i/o interface: biss c protocol 19 interface parameters with biss c protocol . 19 example of biss data output . . . . . . . . 20 register communication . . . . . . . . . . . . 20 internal reset function . . . . . . . . . . . . 20 short biss timeout . . . . . . . . . . . . . . 20 i/o interface: ssi protocol 22 examples of ssi data output . . . . . . . . 23 eeprom interface 24 example of crc calculation routine . . . . . 24 startup behavior 25 application notes 26 principle input circuits . . . . . . . . . . . . . 26 basic circuit . . . . . . . . . . . . . . . . . . . 27 evaluation board 27 design review: function notes 28 p r e l i m i n a r y p r e l i m i n a r y
ic-nqc 13-bit sin/d converter with signal calibration rev d1, page 4/ 29 packages tssop20 (according to jedec standard) pin configuration tssop20 4.4 mm, lead pitch 0.65 mm pin functions no. name function 1 pcos input cosine + 2 ncos input cosine - 3 vdda +5 v supply voltage (analog) 4 gnda ground (analog) 5 vref reference voltage output 6 a incremental output a analog signal cos+ (tma mode) pwm signal for offset sine (calib.) 7 b incremental output b analog signal cos- (tma mode) pwm signal for offset cosine (calib.) 8 z incremental output z pwm signal for phase/ratio (calib.) 9 gnd ground 10 vdd +5 v supply voltage (digital) 11 sli i/o interface, data input* 12 ma i/o interface, clock line 13 slo i/o interface, data output 14 sda eeprom interface, data line analog signal sin+ (tma mode) 15 scl eeprom interface, clock line analog signal sin- (tma mode) 16 nerr error input/output, active low 17 pzero input zero signal + 18 nzero input zero signal - 19 psin input sine + 20 nsin input sine - external connections linking vdda to vdd and gnd to gnda are required. *) if only a single ic-nqc is used and no chain circuitry of multiple biss slaves, pin sli can remain unwired or can be linked to ground (gnd). p r e l i m i n a r y p r e l i m i n a r y
ic-nqc 13-bit sin/d converter with signal calibration rev d1, page 5/ 29 absolute maximum ratings these ratings do not imply permissible operating conditions; functional operation is not guaranteed. exceeding these ratings may damage the device. item symbol parameter conditions unit no. min. max. g001 vdda voltage at vdda -0.3 6 v g002 vdd voltage at vdd -0.3 6 v g003 vpin() voltage at psin, nsin, pcos, ncos, pzero, nzero, vref, nerr, scl, sda, ma, sli, slo, a, b, z v() < vdda + 0.3 v -0.3 6 v v() < vdd + 0.3 v g004 imx(vdda) current in vdda -50 50 ma g005 imx(gnda) current in gnda -50 50 ma g006 imx(vdd) current in vdd -50 50 ma g007 imx(gnd) current in gnd -50 50 ma g008 imx() current in psin, nsin, pcos, ncos, pzero, nzero, vref, nerr, scl, sda, ma, sli, slo, a, b, z -10 10 ma g009 ilu() pulse current in all pins (latch-up strength) according to jedec standard no. 78; -100 100 ma ta = 25 c, pulse duration to 10 ms, vdda = vdda max , vdd = vdd max , vlu() = (-0.5...+1.5) x vpin() max g010 vd() esd susceptibility at all pins hbm 100 pf discharged through 1.5 k
2 kv g011 tj junction temperature -40 150 c g012 ts storage temperature range -40 150 c thermal data operating conditions: vdda = vdd = 5 v 10 % item symbol parameter conditions unit no. min. typ. max. t01 ta operating ambient temperature range (extended temperature range of -40 to 125 c available on request) -25 85 c all voltages are referenced to ground unless otherwise stated. all currents ?owing into the device pins are positive; all currents ?owing out of the device pins are negative. p r e l i m i n a r y p r e l i m i n a r y
ic-nqc 13-bit sin/d converter with signal calibration rev d1, page 6/ 29 electrical characteristics operating conditions: vdda = vdd = 5 v 10 %, tj = -40 ... 125 c, unless otherwise stated. item symbol parameter conditions unit no. min. typ. max. total device functionality and parameters beyond the operating conditions (with reference to independent voltage supplies, for instance) are to be veri?ed within the individual application using fmea methods. 001 vdda, vdd permissible supply voltage 4.5 5.5 v 002 i(vdda) supply current in vdda ?n() = 200 khz; a, b, z open 15 ma 003 i(vdd) supply current in vdd ?n() = 200 khz; a, b, z open 20 ma 004 von turn-on threshold vdda, vdd 3.2 4.4 v 005 vhys turn-on threshold hysteresis 200 mv 006 vc()hi clamp voltage hi at psin, nsin, pcos, ncos, pzero, nzero, vref vc()hi = v() - vdda; 0.3 1.6 v i() = 1 ma, other pins open 007 vc()lo clamp voltage lo at psin, nsin, pcos, ncos, pzero, nzero, vref, nerr, scl, sda, ma, sli, slo, a, b, z i() = -1 ma, other pins open -1.6 -0.3 v 008 vc()hi clamp voltage hi at nerr, scl, sda, ma, sli, slo, a, b, z vc()hi = v() - vdd; 0.3 1.6 v i() = 1 ma, other pins open input ampli?ers and signal inputs psin, nsin, pcos, ncos 101 vos() input offset voltage vin() and g() in accordance with table gain; g 20 -10 10 mv g < 20 -15 15 mv 102 tcos input offset voltage temperature drift see 101 10 v/k 103 iin() input current v() = 0 v ... vdda -50 50 na 104 ga gain accuracy g() in accordance with table gain 95 102 % 105 garel gain sin/cos ratio accuracy g() in accordance with table gain 97 103 % 106 fhc cut-off frequency g = 80 150 khz g = 2.667 630 khz 107 sr slew rate g = 80 2.3 v/s g = 2.667 8.0 v/s sine-to-digital conversion 201 aaabs absolute angle accuracy without calibration referred to 360 input signal, g = 2.667, vin = 1.5 vpp, hys = 0 -1.0 1.0 deg 202 aaabs absolute angle accuracy after calibration referred to 360 input signal, hys = 0, internal signal amplitude of 2 ... 4 vpp -0.5 0.35 +0.5 deg 203 aarel relative angle accuracy referred to signal periods at a, resp. b (see fig. 1); -10 10 % g = 2.667, vin = 1.5 vpp, selres = 1024, fctr = 0x0004 ... 0x00ff, ?n < ?n max (see table 15 ) reference voltage output vref 801 vref reference voltage i(vref) = -1 ma ... +1 ma 48 52 % vdda oscillator a01 fosc()max permissible max. oscillator frequency presented at pin scl with subdivision 90 mhz of 2048; a02 fosc() oscillator frequency presented at pin scl with subdivision of 2048; vdda = vdd = 5 v 10 % 56 90 mhz vdda = vdd = 5 v 60 74 85 mhz a03 tcosc oscillator frequency tempera- ture drift vdda = vdd = 5 v -0.1 %/k a04 vcosc oscillator frequency power sup- ply dependance +9 %/v p r e l i m i n a r y p r e l i m i n a r y
ic-nqc 13-bit sin/d converter with signal calibration rev d1, page 7/ 29 electrical characteristics operating conditions: vdda = vdd = 5 v 10 %, tj = -40 ... 125 c, unless otherwise stated. item symbol parameter conditions unit no. min. typ. max. zero signal enable inputs pzero, nzero b01 vos() input offset voltage v() = vcm() -20 20 mv b02 iin() input current v() = 0 v ... vdda -50 50 na b03 vcm() common-mode input voltage range 1.4 vdda- 1.5 v b04 vdm() differential input voltage range 0 vdda v incremental outputs a, b, z and i/o interface output slo d01 vs()hi saturation voltage hi vs()hi = vdd - v(); i() = -4 ma 0.4 v d02 vs()lo saturation voltage lo i() = 4 ma 0.4 v d03 tr() rise time cl() = 50 pf 60 ns d04 tf() fall time cl() = 50 pf 60 ns d05 rl() permissible load at a, b tma = 1 (calibration mode) 1 m
i/o interface inputs ma, sli e01 vt()hi threshold voltage hi 2 v e02 vt()lo threshold voltage lo 0.8 v e03 vt()hys hysteresis vt()hys = vt()hi - vt()lo 300 mv e04 ipu(ma) pull-up current in ma v() = 0 ... vdd - 1 v -240 -120 -25 a e05 ipd(sli) pull-down current in sli v() = 1 ... vdd 20 120 300 a e06 fclk(ma) permissible ma clock frequency ssi protocol 4 mhz biss protocol 10 mhz e07 tp(ma- slo) propagation delay: ma edge vs. slo output rl(slo) 1 k
10 50 ns e08 tbusy_s processing time single-cycle data (delay of start bit) 0 s e09 tbusy_r processing time register ac- cess (delay of start bit) with read access to eeprom 2 ms e10 tidle interface blocking time powering up with no eeprom 1 1.5 ms e11 t_tos timeout timo = 0, toa =0 20 s eeprom interface inputs sda and error input nerr f01 vt()hi threshold voltage hi 2 v f02 vt()lo threshold voltage lo 0.8 v f03 vt()hys hysteresis vt()hys = vt()hi - vt()lo 300 mv f04 tbusy()cfg duration of startup con?guration error free eeprom access 5 7 ms eeprom interface outputs sda, scl and error output nerr g01 f() write/read clock at scl 20 100 khz g02 vs()lo saturation voltage lo i() = 4 ma 0.45 v g03 ipu() pull-up current v() = 0 ... vdd - 1 v -600 -300 -75 a g04 ft() fall time cl() = 50 pf 60 ns g05 tmin()lo min. duration of error indication at nerr (lo signal) ma = hi, no biss access, amplitude or frequeny error 10 ms g06 tpwm() cycle duration of error indica- tion at nerr fosc() subdivided 2 22 60.7 ms g07 t()lo duty cycle of error indication at nerr signal duration low to high; aerr = 0 (amplitude error) 75 % ferr = 0 (frequency error) 50 % g08 rl() permissible load at sda, scl tma = 1 (calibration mode) 1 m
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ic-nqc 13-bit sin/d converter with signal calibration rev d1, page 8/ 29 electrical characteristics operating conditions: vdda = vdd = 5 v 10 %, tj = -40 ... 125 c, unless otherwise stated. item symbol parameter conditions unit no. min. typ. max. signal monitoring h01 vth voltage threshold for monitoring of minimal amplitude vdda = 5 v, selampl = 0, ampl = 0x00, phi: 0, 90, 180, 270 2.8 3.0 3.2 v ampl = 0x01, phi: 0 3.0 3.2 3.4 v ampl = 0x02, phi: 0 3.2 3.4 3.6 v ampl = 0x03, phi: 0 3.4 3.6 3.8 v h02 vthmax upper voltage threshold for monitoring of sin 2 +cos 2 vdda = 5 v, selampl = 1, ampl = 0x04...0x07, phi: 0, 45...315 3.45 4.5 4.8 v h03 vthmin lower voltage threshold for monitoring of sin 2 +cos 2 vdda = 5 v, selampl = 1, ampl = 0x04, phi: 0, 45...315 0.2 1.0 1.5 v ampl = 0x05, phi: 45 0.6 1.5 2.0 v ampl = 0x06, phi: 45 1.1 2.0 2.5 v ampl = 0x07, phi: 45 1.7 2.5 3.0 v characteristics: diagrams figure 1: de?nition of relative angle error and minimum transition distance figure 2: typical residual absolute angle error after calibration. p r e l i m i n a r y p r e l i m i n a r y a b t ab t mtd t whi t aarel aarel 0 90 180 270 360 -0.15 -0.1 -0.05 0 0.05 0.1 0.15
ic-nqc 13-bit sin/d converter with signal calibration rev d1, page 9/ 29 operating requirements: i/o interface operating conditions: vdd = 5 v 10 %, ta = -25 ... 85 c; input levels lo = 0 ... 0.45 v, hi = 2.4 v ... vdd item symbol parameter conditions fig. unit no. min. max. ssi protocol i001 t mas permissible clock period t tos according to table 44 4 250 2x t tos ns i002 t mash clock signal hi level duration 4 25 t tos ns i003 t masl clock signal lo level duration 4 25 t tos ns biss c protocol i004 t mas permissible clock period t tos according to table 34 5 100 2x t tos ns i005 t mash clock signal hi level duration 5 25 t tos ns i006 t masl clock signal lo level duration 5 25 t tos ns figure 3: timing diagram in ssi protocol. figure 4: timing diagram in biss c protocol. p r e l i m i n a r y p r e l i m i n a r y
ic-nqc 13-bit sin/d converter with signal calibration rev d1, page 10/ 29 parameter and register register description, overview . . . . . . . . . . . page 10 signal conditioning . . . . . . . . . . . . . . . . . . . . . . . page 11 gain: gain select sinoffs: offset calibration sine cosoffs: offset calibration cosine refoffs: offset calibration reference ratio: amplitude calibration phase: phase calibration converter function . . . . . . . . . . . . . . . . . . . . . . . . page 12 selres: resolution hys: hysteresis fctr: max. permissible converter frequency incremental signals . . . . . . . . . . . . . . . . . . . . . . . page 15 cfgabz: output a, b, z rot: direction of rotation cbz: 24-bit period counter con?guration enresdel: output delay a, b, z zpos: zero signal position cfgz: zero signal length cfgab: zero signal logic signal monitoring and error messages . . . . . . . . . . . . . . . . . . . . . . . page 17 selampl: amplitude monitoring, function ampl: amplitude monitoring, thresholds aerr: amplitude error ferr: frequency error test functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 18 tmode: test mode tma: analog test mode biss interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 19 selssi: protocol version timo, toa: timeout tos: timeout short** m2s: data output and options crc6: crc polynomial nzb: zero bit encds: protocol options rpl: register protection settings gray: ssi data format overview adr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00 encds m2s(1:0) selres(4:0) 0x01 hys(2:0) zpos(4:0) 0x02 enresdel selssi rot cbz cfgabz(1:0) cfgz(1:0) 0x03 crc6 nzb cfgab(1:0) rpl 0 aerr ferr 0x04 fctr(7:0) 0x05 gray fctr(14:8) 0x06 reserved* timo 0 tmode(2:0) tma 0x07 reserved* toa reserved* 0x08 gain(3:0) ratio(3:0) 0x09 sinoffs(7:0) 0x0a cosoffs(7:0) 0x0b phase(5:0) refoffs ratio(4) 0x0c reserved* selampl ampl(1:0) 0x0d 0x0e 0x0f crc_e2p(7:0) - check value read from the eeprom for addresses 0x00 to 0x0e eeprom 0x10 - 0x1f 0x00 - 0x0f reserved eeprom memory section: ic-nqc device con?guration data. 0x41 - 0x7f 0x31 - 0x6f reserved eeprom memory section: biss c slave registers (device identi?er 4e 51 43 35 00 00 69 43) register contents are random when powering up without an eeprom. when no register protection is active, all registers permit read and write access (see rpl). *) reserved registers must be programmed to zero. **) for tos see table 42 on page 21 . table 5: register layout p r e l i m i n a r y p r e l i m i n a r y
ic-nqc 13-bit sin/d converter with signal calibration rev d1, page 11/ 29 signal conditioning input stages sin and cos are con?gured as instru- mentation ampli?ers. the ampli?er gain must be se- lected in accordance with the input signal amplitude and programmed to register gain according to the fol- lowing table. half of the supply voltage is available at vref as a center voltage to enable the dc level to be adapted. gain adr 0x08, bit 7:4 sine/cosine input signal levels vin() amplitude average value (dc) code ampli?cation differential single-ended differential single-ended 0x0f 80.000 up to 50 mvpp up to 100 mvpp 0.7 v ... vdda - 1.2 v 0.8 v ... vdda - 1.2 v 0x0e 66.667 up to 60 mvpp up to 120 mvpp 0.7 v ... vdda - 1.2 v 0.8 v ... vdda - 1.2 v 0x0d 53.333 up to 75 mvpp up to 0.15 vpp 0.7 v ... vdda - 1.2 v 0.8 v ... vdda - 1.2 v 0x0c 40.000 up to 0.1 vpp up to 0.2 vpp 1.2 v ... vdda - 1.2 v 1.3 v ... vdda - 1.3 v 0x0b 33.333 up to 0.12 vpp up to 0.24 vpp 1.2 v ... vdda - 1.2 v 1.3 v ... vdda - 1.3 v 0x0a 28.571 up to 0.14 vpp up to 0.28 vpp 0.7 v ... vdda - 1.2 v 0.8 v ... vdda - 1.3 v 0x09 26.667 up to 0.15 vpp up to 0.3 vpp 1.2 v ... vdda - 1.2 v 1.3 v ... vdda - 1.3 v 0x08 20.000 up to 0.2 vpp up to 0.4 vpp 0.7 v ... vdda - 1.2 v 0.8 v ... vdda - 1.3 v 0x07 14.287 up to 0.28 vpp up to 0.56 vpp 1.2 v ... vdda - 1.3 v 1.4 v ... vdda - 1.4 v 0x06 10.000 up to 0.4 vpp up to 0.8 vpp 1.2 v ... vdda - 1.3 v 1.4 v ... vdda - 1.5 v 0x05 8.000 up to 0.5 vpp up to 1 vpp 0.8 v ... vdda - 1.4 v 1.0 v ... vdda - 1.6 v 0x04 6.667 up to 0.6 vpp up to 1.2 vpp 0.8 v ... vdda - 1.4 v 1.1 v ... vdda - 1.7 v 0x03 5.333 up to 0.75 vpp up to 1.5 vpp 0.9 v ... vdda - 1.5 v 1.3 v ... vdda - 1.9 v 0x02 4.000 up to 1 vpp up to 2 vpp 1.2 v ... vdda - 1.6 v 1.7 v ... vdda - 2.1 v 0x01 3.333 up to 1.2 vpp up to 2.4 vpp 1.2 v ... vdda - 1.7 v 1.8 v ... vdda - 2.3 v 0x00 2.667 up to 1.5 vpp up to 3 vpp 1.3 v ... vdda - 1.8 v 2.0 v ... vdda - 2.6 v table 6: input gain sinoffs adr 0x09, bit 7:0 cosoffs adr 0x0a, bit 7:0 code output offset input offset 0x00 0 v 0 v 0x01 -7.8125 mv -7.8125* mv / gain ... ... ... 0x7f -0.9922 v -0.9922 v / gain 0x80 0 v 0 v 0x81 +7,8125 mv +7.8125 mv / gain ... ... ... 0xff +0.9922 v +0.9922 v / gain notes *) with refoffs = 0x00 and vdda = 5 v. table 7: sine/cosine offset calibration refoffs adr 0x0b, bit 1 code reference voltage 0x00 dependent on vdda (example of application: mr sensors) 0x01 not dependent on vdda (example of application: sin/cos encoders) table 8: offset reference ratio adr 0x0b, bit 0, adr 0x08, bit 3:0 code cos / sin code cos / sin 0x00 1.0000 0x10 1.0000 0x01 1.0067 0x11 0.9933 ... ... ... ... 0x0f 1.1 0x1f 0.9000 table 9: amplitude calibration phase adr 0x0b, bit 7:2 code phase shift code phase shift 0x00 90 0x20 90 0x01 90.703125 0x21 89.296875 ... ... ... ... 0x12 102.65625 0x32 77.34375 ... 102.65625 ... 77.34375 0x1f 102.65625 0x3f 77.34375 table 10: phase calibration p r e l i m i n a r y p r e l i m i n a r y
ic-nqc 13-bit sin/d converter with signal calibration rev d1, page 12/ 29 converter functions selres adr 0x00, bit 4:0 code binary resolutions examples of permissible input frequencies ?n max (fctr 0x0004, 0x4302) 0x00 - 0x01 - 0x02 - 0x03 8192 158 hz, 1.06 khz 0x04 4096 317 hz, 2.12 khz 0x05 2048 634 hz, 4.24 khz 0x06 1024 1.27 khz, 8.5 khz 0x07 512 2.54 khz, 17 khz 0x08 256 5.1 khz, 34 khz 0x09 128 10.2 khz, 68 khz 0x0a 64 20.3 khz, 136 khz 0x0b 32 40.6 khz (max. 250 khz) 0x0c 16 81.3 khz (max. 250 khz) 0x0d 8 162 khz (max. 250 khz) 0x0e - 0x0f - table 11: binary resolutions selres adr 0x00, bit 4:0 code decimal resolutions examples of permissible input frequencies ?n max (fctr 0x0004, 0x4302) 0x10 2000 650 hz, 4.3 khz 0x11 1600 812 hz, 5.5 khz 0x12 1000 1.3 khz, 8.6 khz 0x13 800 1.6 khz, 10.8 khz 0x14 500 2.6 khz, 17 khz 0x15 400 3.2 khz, 22 khz 0x16 250 *1 5.2 khz, 35 khz 0x17 125 *1,2 5.2 khz, 35 khz 0x18 320 4.1 khz, 27 khz 0x19 160 *2 4.1 khz, 27 khz 0x1a 80 *4 4.1 khz, 27 khz 0x1b 40 *8 4.1 khz, 27 khz 0x1c 200 6.5 khz, 43.3 khz 0x1d 100 *2 6.5 khz, 43.3 khz 0x1e 50 *1,4 6.5 khz, 43.3 khz 0x1f 25 *1,8 6.5 khz, 43.3 khz notes *1 not suitable for incremental output on a, b. *2,4,8 the internal resolution is higher by a factor of 2, 4 or 8. table 12: decimal resolutions hys adr 0x01, bit 7:5 code hysteresis in degrees hysteresis in lsb absolute error* 0x00 0 0x01 0.0879 1 lsb @ 12 bit 0.044 0x02 0.1758 1/2 lsb @ 10 bit 0.088 0x03 0.3516 1 lsb @ 10 bit 0.176 0x04 0.7031 1/2 lsb @ 8 bit 0.352 0x05 1.4063 1 lsb @ 8 bit 0.703 0x06 5.625 2.813 0x07 45 only recommended for calibration 22.5 notes *) the resulting absolute error is equivalent to half the angle hysteresis. table 13: hysteresis p r e l i m i n a r y p r e l i m i n a r y
ic-nqc 13-bit sin/d converter with signal calibration rev d1, page 13/ 29 maximum possible converter frequency the converter frequency automatically adjusts to the value required by the input frequency and resolution. this value ranges from zero to a maximum depen- dent on the oscillator frequency that is set via register fctr. serial data output for biss or ssi output the maximum possible con- verter frequency can be adjusted to suit the maxi- mum input frequency; an automatic converter resolu- tion step-down feature can be enabled via the fctr register. should the input frequency exceed the fre- quency limit of the selected converter resolution, the lsb is kept stable and not resolved any further; the interpolation resolution halves. if the next frequency limit is overshot, the lsb and lsb +1 are kept stable and so on. if the input frequency again sinks below this frequency threshold, ?ne reso- lution automatically returns. with the programming of crc6 = 1 a resolution step- down will be signalled via the biss warning bit. max. possible converter frequency for serial data output resolution protocol max. input frequency restrictions examples* requirements at high input frequency ?n max [khz] at resol. fctr min. res. bin dec biss ssi ?n max 8192 1024 200 0x0004 x x x x fosc()min / 40 / resolution C 0.16 1.27 6.5 0x4102 8 x x x x fosc()min / 24 / resolution rel. angle error 2x increased 0.26 2.1 10.8 0x4202 16 x x x x 2 x fosc()min / 24 / res. rel. angle error 4x increased 0.53 4.2 21.6 0x4302 32 x x x x 4 x fosc()min / 24 / res. rel. angle error 8x increased 1.06 8.5 43.3 0x4702 64 x - x x 8 x fosc()min / 24 / res. resolution lowered by factor of 2 2.1 16.9 - 0x4b02 128 x - x x 16 x fosc()min / 24 / res. res. lowered by factor of 2-4 4.2 33.8 - 0x4f02 256 x - x x 32 x fosc()min / 24 / res. res. lowered by factor of 2-8 8.5 67.7 - 0x5302 512 x - x x 64 x fosc()min / 24 / res. res. lowered by factor of 2-16 16.9 135 - 0x5702 1024 x - x x 128 x fosc()min / 24 / res. res. lowered by factor of 2-32 33.8 250 - 0x5b02 2048 x - x x 256 x fosc()min / 24 / res. res. lowered by factor of 2-64 67.7 - - 0x5f02 4096 x - x x 512 x fosc()min / 24 / res. res. lowered by factor of 2-128 135 - - 0x6302 8192 x - x x 1024 x fosc()min / 24 / res. res. lowered by factor of 2-256 250 - - notes *) calculated with fosc()min taken from electrical characteristics, item a01. table 14: maximum converter frequency for serial data output. p r e l i m i n a r y p r e l i m i n a r y
ic-nqc 13-bit sin/d converter with signal calibration rev d1, page 14/ 29 incremental output to a, b and z settings for the maximum possible converter fre- quency using register fctr are governed by two cri- teria: 1. the maximum input frequency 2. system restrictions caused by slow counters or data transmission via cable in this case it is sensible to preselect a minimum tran- sition distance for the output signals. these settings also make a suitable zero-delay digital glitch ?lter that acts on esd impact on the sensor and keeps the out- put signals spike free through temporal separation, for example. serial data output is possible at any time in biss or ssi protocol. however, for the transfer of angle data to the output register the incremental output is halted for one period of the clock signal at pin ma. 1. max. possible converter frequency de?ned by the maximum input frequency output frequency resolution maximum input frequency restrictions examples* fout @ ?n max requirem. at high input frequency ?n max [khz] at resol. fctr a, b bin dec ?n max 8192 1024 200 0x0004 325 khz x x fosc()min / 40 / resolution none 0.16 1.27 6.5 0x4102 542 khz x x fosc()min / 24 / resolution relative angle error 2x increased 0.26 2.1 10.8 0x4202 1.08 mhz x x 2 x fosc()min / 24 / res. relative angle error 4x increased 0.53 4.2 21.6 0x4302 2.17 mhz x x 4 x fosc()min / 24 / res. relative angle error 8x increased 1.06 8.5 43.3 notes *) calculated with fosc()min taken from electrical characteristics, item a01. table 15: maximum possible converter frequency for incremental a/b/z output, de?ned by the maximum input frequency 2. max. possible converter frequency de?ned by the minimum transition distance output frequency resolution minimum transition distance restrictions example* fout @ t mtd requirem. at a, b at high input frequency t mtd [sec] fctr a, b bin dec t mtd 0x00ff 11 khz x x 2048 / fosc()max none 22.8 0x00fe 11.03 khz x x 2040 / fosc()max none 22.7 0x00fd 11.07 khz x x 2032 / fosc()max none 22.6 ... ... ... ... ... ... ... 0x0006 402 khz x x 56 / fosc()max none 0.62 0x0005 536 khz x x 48 / fosc()max none 0.53 0x0004 562 khz x x 40 / fosc()max none 0.44 0x4102 938 khz x x 24 / fosc()max relative angle error 2x increased 0.27 0x4202 1.87 mhz x x 12 / fosc()max relative angle error 4x increased 0.13 0x4302 3.75 mhz x x 6 / fosc()max relative angle error 8x increased 0.07 notes *) calculated with fosc()max taken from el.char., item a01; transition distance output a vs. output b with same direction of rotation. table 16: maximum possible converter frequency for incremental a/b/z output, de?ned by the minimum transition distance p r e l i m i n a r y p r e l i m i n a r y
ic-nqc 13-bit sin/d converter with signal calibration rev d1, page 15/ 29 incremental signals cfgabz adr 0x02, bit 3:2 code mode pin a pin b pin z 0x00 normal a b z 0x01 control signals for external period counters ca cb cz 0x02 calibration mode offset+phase the following settings are required additionally: selres = 0x0d zpos = 0x00 hys = 0x07 rot = 0x00 cfgab = 0x00 aerr = 0x00 figure 5: offset sin* figure 6: offs. cos* figure 7: phase* 0x03 calibration mode offset+amplitude the following settings are required additionally: selres = 0x0d zpos = 0x00 hys = 0x07 rot = 0x00 cfgab = 0x00 aerr = 0x00 figure 8: offset sin* figure 9: offs. cos* figure 10: amplit.* notes *) trimmed accurately when duty cycle is 50 %; recommended trimming order (after selecting gain): offset, phase, amplitude ratio, offset; table 17: outputs a, b, z rot adr 0x02, bit 5 code code direction 0x00 ascending order, b then a 0x01 descending order, a then b table 18: code direction cbz adr 0x02, bit 4 code reset via zero 0x00 not activated 0x01 activated table 19: reset enable for period counter enresdel adr 0x02, bit 7 code output* function 0x00 immediately an external counter displays the absolute angle following power-on. 0x01 after 5 ms an external counter only displays changes vs. the initial power-on (conditional on standby at power-on) notes *) output delay after device con?guration and internal reset (a, b, z remains on high). table 20: output delay a, b, z figure 11: period counter reset by zero signal (en- abled by cbz = 1). example gives a resolution of 64 (selres = 0x0a), a zero signal at 45 (zpos = 0x04, cfgab = 0x00) and no inversion of the direction of rotation (rot = 0x00, cos leads sin). p r e l i m i n a r y p r e l i m i n a r y -180 -90 0 45 90 180 sin cos 000000 ab z p(23:0) ccw: 0->f ffffff cw: f->0
ic-nqc 13-bit sin/d converter with signal calibration rev d1, page 16/ 29 zpos adr 0x01, bit 4:0 code position 0x00 0 0x08 90 0x10 180 0x18 270 0x01 11.25 (1 x 11.25) ... ... 0x1f 348.75 (31 x 11.25) notes the zero signal is only output if released by the input pins (for instance with pzero = 5 v, nzero = vref). table 21: zero signal position cfgz adr 0x02, bit 1:0 code length 0x00 90 0x01 180 0x02.. 03 synchronization table 22: zero signal length cfgab adr 0x03, bit 5:4 code z = 1 for 0x00 b = 1, a = 1 0x01 b = 0, a = 1 0x02 b = 1, a = 0 0x03 b = 0, a = 0 table 23: zero signal logic figure 12: incremental output signals for various zero signal lengths. example gives a resolution of 64 (selres = 0x0a), a zero signal position of 45 (zpos = 0x04, cfgab = 0x00) and no inversion of the direction of rotation (rot = 0x00, cos leads sin). p r e l i m i n a r y p r e l i m i n a r y -180 -90 0 45 90 180 winkel sin cos a b z (cfgz= 1) z (cfgz= 2) z (cfgz= 0)
ic-nqc 13-bit sin/d converter with signal calibration rev d1, page 17/ 29 signal monitoring and error messages selampl ampl adr 0x0c, bit 2 adr 0x0c, bit 1:0 max ( |sin| , |cos| ) for selampl = 0 code voltage threshold v th output amplitude* 0x00 0.60 x vdda 1.4 v pp 0x01 0.64 x vdda 2.0 v pp 0x02 0.68 x vdda 2.6 v pp 0x03 0.72 x vdda 3.1 v pp sin 2 + cos 2 for selampl = 1 code v thmin $ v thmax output amplitude* 0x04 (0.20 $ 0.9) x vdda 1.0 v pp $ 4.5 v pp 0x05 (0.30 $ 0.9) x vdda 1.5 v pp $ 4.5 v pp 0x06 (0.40 $ 0.9) x vdda 2.0 v pp $ 4.5 v pp 0x07 (0.50 $ 0.9) x vdda 2.5 v pp $ 4.5 v pp notes v th , v thmin , v thmax are typical values; refer to elec. char. no. h01 cf. for maximal values. *) entries are calculated with vdda = 5 v. table 24: signal amplitude monitoring aerr adr 0x03, bit 1 code amplitude error message 0x00 disabled 0x01 enabled table 25: amplitude error ferr adr 0x03, bit 0 code excessive frequency error message 0x00 disabled 0x01 enabled notes input frequency monitoring is operational for resolutions 16 table 26: frequency error con?guration error - always enabled table 27: con?guration error error indication at nerr failure mode pin signal nerr no error hi amplitude error lo/hi = 75 % (resp. hi for aerr = 0) frequency error lo/hi = 50 % (resp. hi for ferr = 0) con?guration lo undervoltage lo system error nerr = low caused by an external error signal table 28: error indication at nerr figure 13: signal monitoring at minimum amplitude. figure 14: sin 2 + cos 2 signal monitoring. error messages failure mode error bits e1, e0 for biss and ssi crc6 = 0 error bits ne, nw for biss and ssi crc6 = 1 no error 1, 1 1, nw amplitude error 0, 1 0, nw frequency error 1, 0 0, nw system error* 0, 0 0, nw warning** ne, 0 notes *system error nerr pulled low by external signal **warning automatic step-back of resolution line signal slo data output is deactivated and slo permanently high in case of: con?guration phase, invalid con?guration, undervoltage. table 29: error messages to enable the diagnosis of faults, the various types of error are signaled at nerr using a pwm code as given in the key on the left. two error bits are provided to enable communication via the i/o interface; these bits can decode four differ- ent types of error. if nerr is held at low by an external source, such as an error message from the system, for example, this can also be veri?ed via the i/o interface. error are stored until the sensor data is output via the i/o interface and then deleted. errors at nerr are displayed for a minimum of ca. 10 ms unless they are deleted beforehand by a data output. p r e l i m i n a r y p r e l i m i n a r y vss vth vthmin vthmax
ic-nqc 13-bit sin/d converter with signal calibration rev d1, page 18/ 29 if an error in amplitude occurs, conversion is termi- nated and the incremental output signals halted. an error in amplitude rules out the possibility of an error in frequency. test functions tmode adr 0x06, bit 3:1 code signal at z description 0x00 z no test mode 0x01 a xor b output a exor b 0x02 enclk ic-haus device test 0x03 nlock ic-haus device test 0x04 clk ic-haus device test 0x05 divc ic-haus device test 0x06 pzero - nzero ic-haus device test 0x07 tp ic-haus device test condition cfgabz = 0x00 table 30: test mode tma adr 0x06, bit 0 code pin a pin b pin sda pin scl 0x00 a b sda scl 0x01 cos+ cos- sin+ sin- notes to permit the veri?cation of gain and offset settings, signals are output after the input ampli?er. a converter signal of 4 vpp is the ideal here and should not be exceeded. pin loads above 1 m
are adviceable for accurate measurements. eeprom access is not possible during mode tma. table 31: analog test mode figure 15: calibrated signals in tma mode. the signal is set to ca. 4 vpp using gain and must not be altered after calibration. both display modes are suitable for offs (positive values) and ratio adjust- ments; x/y mode is preferable for phase. test signals cos- (pin b) and sin- (pin scl) must be selected to set negative values for offs. p r e l i m i n a r y p r e l i m i n a r y sda: sin+ a: cos+ 5 v x/y 0 v 1 v/div vert. 1 v/div hor. y/t 1 v/div vert.
ic-nqc 13-bit sin/d converter with signal calibration rev d1, page 19/ 29 i/o interface: biss c protocol the serial i/o interface operates in biss c protocol mode and enables sensor data to be output in uninter- ruptible cycles (data channel scd). at the same time parameters can be exchanged via bidirectional register communication (data channel cd). the sensor data produced by ic-nqc contains the an- gle value (s) with 3 to 13 bits, the period count (p) with 0, 8, 12 or 24 bits, two error bits (e1 and e0) and 5 or 6 crc bits (crc). figure 16: example line signals (biss c) single cycle data channel: scd bits typ label 0...24 data period counter p(23:0): 0, 8, 12, 24 bit (multiturn position) 3...13 data angle data s(12:0): 3 bis 13 bit (singleturn position) 1 error error bit e1 (amplitude error) 1 error error bit e0 (frequency error) 5...6 crc polynomial 0x25 x 5 + x 2 + x 0 (inverted bit output) - oder - polynomial 0x43 x 6 + x 1 + x 0 (inverted bit output) table 32: biss data channels interface parameters with biss c protocol selssi adr 0x02, bit 6 code protocol information 0 1 biss c ssi www.biss-interface.com table 33: protocol version timo adr 0x06, bit 5 code clock timeout t tos fclk(ma) min* 0 46-47 ca. 20 s 50 khz 1 3-4 ca. 1.5 s 660 khz toa addr 0x07, bit 3 0 see timo 1 adaptive with t clk = 42/fosc see biss speci?cation 50 khz notes a ref. clock count is equal to 32 fosc (see el. char., a02). the permissible max. clock frequency is speci?ed by e06. *) a low clock frequency can reduce the permissible maximum input frequency since conversion is paused for one ma cycle from latch onwards. table 34: timeout con?guration (protectable) m2s adr 0x00, bit 6:5 code data length crc polynomial 0x00 - 0x25 (with crc6 = 0) 0x01 p(7:0) 0x25 (with crc6 = 0) 0x02 p(11:0) 0x43 0x03 p(23:0) 0x43 table 35: period counter output crc6 adr 0x03, bit 7 code crc polynomial status messages 0 determined by m2s e1, e0 1 0x43 ne, nw table 36: crc polynomial p r e l i m i n a r y p r e l i m i n a r y
ic-nqc 13-bit sin/d converter with signal calibration rev d1, page 20/ 29 nzb adr 0x03, bit 6 code function 0 zero bit 1 no zero bit notes the optional zero bit is output as the ?nal bit after the crc. table 37: zero bit encds adr 0x00, bit 7 code description 0x00 data output biss b or ssi 0x01 data output biss c table 38: protocol options m2s can be used to set the number of period counter bits sent as sensor data. the counter bits are trans- mitted before the angle value, with the msb leading. the 5-bit crc output is based on polynomial 0x25 (100101b), with the 6-bit crc output based on poly- nomial 0x43 (1000011b) automatically coming active with longer scd data, or when preselected by crc6. as a rule, crc bits are sent inverted. an additional zero bit can be output following the crc bits. however, disabling the zero bit by nzb = 1 is rec- ommended when the output data length does not need to comply with existing applications. to obtain a position data output being compatible to the biss b protocol parameter encds = 0 does switch off the cds bit, without a replacement by a zero bit. thus, the output data length is shorten by one bit and register communication is limited to the direction of the master to the slave. the bidirectional biss c register commu- nication must be enabled by setting encds = 1. example of biss data output scd: angle data bits typ label 12 data angle data s(11:0) 2 error error ne and warning nw 6 crc polynomial 0x43 con?g. selres = 0x04, m2s = 0x00, crc6 = 1, nzb = 1 table 39: example format 1 for biss pro?le bp1 scd: angle data with 8-bit period count bits type label 8 data period counter p(7:0) 13 data angle data s(12:0) 2 error error bits e1, e0 5 crc polynomial 0x25 1 zero zero bit con?g. selres = 0x03, m2s = 0x01, crc6 = 0, nzb = 0 table 40: example format 2 scd: angle data with 24-bit period count bits type label 24 data period counter p(23:0) 13 data angle data s(12:0) 2 error error bits e1, e0 6 crc polynomial 0x43 (no zero bit) con?g. selres = 0x03, m2s = 0x03, crc6 = 0, nzb = 1 table 41: example format 3 register communication after the biss c protocol slave registers are directly addressed in a reserved address area (0x40 to 0x7f). other storage areas are addressed dynamically and in blocks. biss addresses 0x00 to 0x3f aim for a reg- ister bank consisting of 64 bytes, the physical storage address of which is determined by bank select n. ic-nqc supports up to 16 storage banks, making it possible to use an 8-bit eeprom to its full capacity. there is therefore also enough storage space for an id plate (eds) and oem data. information regarding memory map and addressing via biss is given on page 25 ). internal reset function a write access at ram address 0x00 (biss address 0x00 with bank select n = 0) triggers an internal reset. based on the current con?guration in the ram, ic- nqc restarts without reading the eeprom. the con- ?gured interface timeout and write protect settings be- come active, the period counter is set to zero and any stored con?guration errors are deleted. the data out- put via slo and the incremental signals at a, b and z are released. providing no amplitude error is present, the converter again counts up from an angle value of zero to the current angle position. short biss timeout for programming via the i/o interface ic-nqc has a short biss timeout function according to the descrip- tion of the biss c protocol (see page 19, table 2, el. char. no. 6). p r e l i m i n a r y p r e l i m i n a r y
ic-nqc 13-bit sin/d converter with signal calibration rev d1, page 21/ 29 regardless of register protection settings a short time- out of typically 1.8 s can be temporarily activated by writing value 0x07 to address 0x7c (address 124d). a controller can then transmit the device con?guration over a shorter period. tos adr 0x7c, bit 2:0 code function 000 regular timeout (con?gured by timo) 001...111 short timeout (equal to timo = 1) table 42: short timeout (via biss device id) the value written to address 0x7c is also transferred to the eeprom, provided an eeprom has been con- nected up and is available. on reading address 0x7c the byte stored in the eep- rom is output as part of the biss device id. here, high-order bits 7:3 are part of the manufacturers id; low-order bits 2:0 act as an indicator of the timeout op- tions (regular or short timeout, see table 42 ). p r e l i m i n a r y p r e l i m i n a r y
ic-nqc 13-bit sin/d converter with signal calibration rev d1, page 22/ 29 i/o interface: ssi protocol ic-nqc can transmit position data in ssi protocol mode; the parameters described in the following give the necessary settings and options. figure 17: example line signal (ssi) selssi adr 0x02, bit 6 code protocol 0 biss c 1 ssi table 43: protocol version timo adr 0x06, bit 5 code timeout t tos fclk(ma)min* 0 long: ca. 20 s 50 khz 1 not permitted toa adr 0x07, bit 3 0 see tos 1 not permitted notes a ref. clock count is equal to 32 fosc (see el. char. a01). the permissible max. clock frequency is speci?ed by item e06. *) a low clock frequency can reduce the permissible maximum input frequency since conversion is paused for one ma cycle from latch onwards. table 44: timeout con?guration for ssi m2s adr 0x00, bit 6:5 code period counter output length 0x00 - 0x01 p(7:0) 0x02 p(11:0) 0x03 p(23:0) table 45: period counter for ssi data output crc6 adr 0x03, bit 7 nzb adr 0x03, bit 6 code additional bits ring operation 0 0 e1, e0 no 0 1 none no 1 0 ne, nw, zero bit yes 1 1 none yes table 46: options for ssi data output gray adr 0x05, bit 7 code ssi data format 0 binary coded 1 gray coded notes data output starts with msb for binary or gray coded data. table 47: ssi data format p r e l i m i n a r y p r e l i m i n a r y
ic-nqc 13-bit sin/d converter with signal calibration rev d1, page 23/ 29 examples of ssi data output ssi output formats 13-bit ssi res mode error crc t1 t2 t3 t4... t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 10 bit ssi x - s9 s8 s7 s6 ... s0 e1 e0 0 stop stop stop stop stop stop stop stop stop stop stop stop example 0 0 0 0 0 0 0 0 0 0 0 0 0 13 bit ssi *1 - - s12 s11 s10 s9 ... s3 s2 s1 s0 stop stop stop stop stop stop stop stop stop stop stop stop example 0 0 0 0 0 0 0 0 0 0 0 0 ssi-r *2 - - s12 s11 s10 s9 ... s3 s2 s1 s0 stop s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 example 0 25-bit ssi 13 bit ssi x - s12 s11 s10 s9 ... s3 s2 s1 s0 e1 e0 0 stop stop stop stop stop stop stop stop stop example 0 0 0 0 0 0 0 0 0 0 8 + 13 bit *3 ssi x - p7 p6 p5 p4 ... p0, s12, s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 e1 e0 0 stop example 0 0 con?guration input sli = 0, selssi = 1, m2s = 0x00, crc6 = 0, nzb = 0, unless otherwise noted. *1) crc6 = 0, nzb = 1; *2) crc6 = 1, nzb = 1; *3) m2s = 0x01 caption ssi = ssi protocol ssi-r = ssi ring operation table 48: ssi transmission formats p r e l i m i n a r y p r e l i m i n a r y
ic-nqc 13-bit sin/d converter with signal calibration rev d1, page 24/ 29 eeprom interface the serial eeprom interface consists of the two pins scl and sda and enables read and write access to a serial eeprom with i 2 c interface (with at least 128 bytes, 5 v type with a 3.3 v function; e.g. 24c01, 24c02, 24c08 and maximal 24c16). the con?guration data in the eeprom, of addresses 0x00 to 0x0f, is secured by a crc check value to ad- dress 0x0f. when the device is powered up, the ad- dress range from 0x00 to 0x0f is mapped onto ic- nqcs con?guration ram. the higher memory area contains biss c slave registers and optional memory banks available to the sensor system. the register access to the con?guration data and the memory banks 1 to 7 (intended for eds) can be re- stricted by parameter rpl. example of crc calculation routine unsigned char ucdatastream = 0 ; i n t icrcpoly = 0x127 ; unsigned char uccrc=0; i n t i = 0 ; uccrc = 0 ; / / s t a r t v a l u e ! ! ! f o r ( ireg = 0 ; ireg <15; ireg ++) { ucdatastream = ucgetvalue ( ireg ) ; f o r ( i =0; i <=7; i ++) { i f ( ( uccrc & 0x80 ) ! = ( ucdatastream & 0x80 ) ) uccrc = (uccrc << 1 ) ^ icrcpoly ; else uccrc = (uccrc << 1 ) ; ucdatastream = ucdatastream << 1 ; } } crc_e2p adr 0x0f, bit 7:0 code description 0x00 ... check value formed by crc polynomial 0x127 0xff table 49: check value for eeprom data register con?guration biss adr hex biss adr decimal contents 0x00...0f 0...15 con?g. data ram (16 bytes) 0x10...1f 16...31 con?g. data eeprom (16 bytes) 0x20...3f 32...63 unused memory area (32 bytes) biss c slave-registers (direct addresses): 0x40 64 bank select (1 byte) 0x41 65 eds bank (1 byte) 0x42...43 66...67 pro?le id (2 bytes) 0x44...47 68...71 serial no. (4 bytes) 0x48...77 72...119 slave registers (48 bytes) device id (6 bytes): 0x78 120 4e (default) 0x79 121 51 (default) 0x7a 122 43 (default) 0x7b 123 31 (default) 0x7c 124 bit 7:3: adr 0x00, bit 2:0: tos 0x7d 125 00 (default) manufacturers id (2 bytes): 0x7e 126 69 (default) 0x7f 127 43 (default) table 50: register overview rpl adr 0x03, bit 3 code bank 0 con?g. dat. 0x40..7f biss id bank 1..7 eds bank 8..15 user data 0x0 read / write read / write read / write read / write 0x1 - read* read read / write notes *) exception: write to 0x40 and 0x7c is always possible. table 51: register protection settings p r e l i m i n a r y p r e l i m i n a r y
ic-nqc 13-bit sin/d converter with signal calibration rev d1, page 25/ 29 figure 18: registers and addressing startup behavior after the supply has been turned on (power on reset), ic-nqc reads the con?guration data from the eep- rom and during this phase halts error pin nerr ac- tively on a low signal (open drain output) as well as data output slo and the incremental signals at a, b and z on a high signal. only after a successful crc the data output to slo and to the a, b, z incremental outputs is released and the error indication at pin nerr reset; an exter- nal pull-up resistor can supply a high signal. ic-nqc then switches to normal operation and determines the current angle position, providing that a sensor is con- nected up to it and there is no amplitude error (or this is deactivated). should the crc prove unsuccessful due to a data er- ror (disrupted transmission, no eeprom or the eep- rom is not programmed), the con?guration phase is automatically repeated. after a third failed attempt, the procedure is aborted and error pin nerr remains ac- tive, displaying a permanent low. after startup, ic-nqc does not recognize a de?ned con?guration; the con?guration ram can contain any values. so that it is always possible to con?gure the setup us- ing the i/o interface - even without an eeprom - ic- nqc ?rst ignores parameters timo, toa and rpl. the i/o interface can then be addressed in biss c protocol with the longest timeout (30 s maximum), without safety settings being observed (cf. rpl = 0x0).this allows the con?guration to be written to ram addresses 0x01 to 0x0c and to address 0x00. ad- dress 0x00 must be written to last of all and triggers an internal reset (see description on page 20 ). a short timeout of 3 s maximum can be temporar- ily activated by writing value 0x07 to address 0x7c (address 124d) to keep the device con?guration time shorter. when operated without an eeprom, ic-nqc does not respond to higher addresses - with the exception of the biss addresses reserved for manufacturers and device ids (0x78 to 0x7f). this address area supplies the chip version from the rom. p r e l i m i n a r y p r e l i m i n a r y 0x30 0x00 0x0f 0x10 0x3f 0x40 0x41 0x42 0x43 0x44 0x47 0x48 0x77 0x78 0x7d 0x7e 0x7f 0x00 0x3f 0x1f 0x20 eds bank profile id serial number device id manufact. id slave register bank 1 bank 2 bank 3 bank 0 bank 15 bank ...14 n = 1 n = 0 n = 2 n = 3 n = ...14 n = 15 bank selection ? n 0x00 0x0f 0x10 0x80 0xbf 0xc0 0xff 0x100 0x13f 0x70 0x7f 0x2f 0x31 0x32 0x33 0x34 0x37 0x68 0x6d 0x6e 0x6f 0x30 0x38 0x67 0x400 0x43f ...0x3ff not available configuration data not available not available 0x00 0x0f configuration data 0x78 0x7d 0x7e 0x7f rom -16 unused biss eeprom ram 2 k b i t / 2 4 c 0 2 8 k b i t / 2 4 c 0 8 1 6 k b i t / 2 4 c 1 6 r e g i s t e r s ( b a n k n ) d i r e c t a c c e s s r e g i s t e r s register rpl1 r r r/w r/w r/w r/w rpl0 --- r/w bank 1...7 0x41...0x7f bank 0 bank 8...15 protection
ic-nqc 13-bit sin/d converter with signal calibration rev d1, page 26/ 29 application notes principle input circuits figure 19: input circuit for voltage signals of 1 vpp with no ground reference. when ground is not separated the connection nsin to vref must be omitted. figure 20: input circuit for current signals of 11 a with no ground reference. offset calibra- tion is not possible with this circuit. figure 21: input circuit for non-symmetrical voltage or current source signals with ground ref- erence (adaptation via resistors r3, r4). figure 22: simpli?ed input wiring for non- symmetrical voltage signals with ground reference. figure 23: input circuit for complementary low-side current source outputs, such as for op- toencoder ic-wg. figure 24: combined input circuit for 11 a, 1 vpp (with 120
termination) or ttl encoder signals. rs3/4 and cs1 serve as protec- tion against esd and transients. p r e l i m i n a r y p r e l i m i n a r y 1vss to 120 s input sin + - + - psin nsin vref ic-nqc sensor case 120 s rs psin nsin 11app input sin + - + - psin nsin vref ic-nqc sensor case 25k s rs2 psin nsin 25k s rs1 vref nsin + - psin - + input sin ic-nqc + - r2 1k s r4 1k s 1k s r1 v-gen 1vpp r3 1k s nsin vref ic-nqc input sin + - psin - + +5v r001 1k s 1k s r002 2vpp v-gen vref nsin + - psin - + input sin ic-nqc + - r2 10k s in 10app r1 10k s ip 10app gain= 10 + - + - psin nsin vref ic-nqc encoder case 120 s rs2 -ttl or open -sin rs4 5k s 1k s 1k s 47nf rs1 rs3 cs2 220pf cs1 input sin +sin +ttl 5k s 5k s 5k s
ic-nqc 13-bit sin/d converter with signal calibration rev d1, page 27/ 29 basic circuit figure 25: basic circuit for the evaluation of mr bridge sensors. evaluation board ic-nqc comes with a demo board for test purposes. instructions are available separately. p r e l i m i n a r y p r e l i m i n a r y
ic-nqc 13-bit sin/d converter with signal calibration rev d1, page 28/ 29 design review: function notes ic-nqc 2 no. function, parameter/code description and application notes please refer to datasheet release b1. table 52: notes on chip functions regarding ic-nqc chip release 2. ic-nqc 3 no. function, parameter/code description and application notes 1 gray for gray-coded data output clock cycles must be fully completed. an earlier termination results in invalid data for the following read out cycle. 2 startup an invalid crc keeps only slo permanently on high, the incremental output to a, b and z is not blocked. table 53: notes on chip functions regarding ic-nqc chip release 3. ic-nqc 5 no. function, parameter/code description and application notes 1 gray gray-coded data output can be terminated at any time. 2 startup an invalid crc keeps slo and a, b and z permanently on high (until an internal reset). 3 period counting following power-on and after an internal reset the period counter is initialized with a value of zero (as all former chip releases). if an input angle of exactly 0 is applied and a movement towards 270 is following, the period counter counts to the value -1 (former chip releases maintain the value of zero). table 54: notes on chip functions regarding ic-nqc chip release 5. ic-haus expressly reserves the right to change its products and/or speci?cations. an info letter gives details as to any amendments and additions made to the relevant current speci?cations on our internet website www.ichaus.de/infoletter ; this letter is generated automatically and shall be sent to registered users by email. copying C even as an excerpt C is only permitted with ic-haus approval in writing and precise reference to source. ic-haus does not warrant the accuracy, completeness or timeliness of the speci?cation and does not assume liability for any errors or omissions in these materials. the data speci?ed is intended solely for the purpose of product description. no representations or warranties, either express or implied, of merchantability, ?tness for a particular purpose or of any other nature are made hereunder with respect to information/speci?cation or the products to which information refers and no guarantee with respect to compliance to the intended use is given. in particular, this also applies to the stated possible applications or areas of applications of the product. ic-haus conveys no patent, copyright, mask work right or other trade mark right to this product. ic-haus assumes no liability for any patent and/or other trade mark rights of a third party resulting from processing or handling of the product and/or any other use of the product. as a general rule our developments, ips, principle circuitry and range of integrated circuits are suitable and speci?cally designed for appropriate use in technical applications, such as in devices, systems and any kind of technical equipment, in so far as they do not infringe existing patent rights. in principle the range of use is limitless in a technical sense and refers to the products listed in the inventory of goods compiled for the 2008 and following export trade statistics issued annually by the bureau of statistics in wiesbaden, for example, or to any product in the product catalogue published for the 2007 and following exhibitions in hanover (hannover-messe). we understand suitable application of our published designs to be state-of-the-art technology which can no longer be classed as inventive under the stipulations of patent law. our explicit application notes are to be treated only as mere examples of the many possible and extremely advantageous uses our products can be put to. p r e l i m i n a r y p r e l i m i n a r y
ic-nqc 13-bit sin/d converter with signal calibration rev d1, page 29/ 29 ordering information type package order designation ic-nqc tssop20 4.4 mm ic-nqc tssop20 evaluation board ic-nqc eval nq6d for technical support, information about prices and terms of delivery please contact: ic-haus gmbh tel.: +49 (61 35) 92 92-0 am kuemmerling 18 fax: +49 (61 35) 92 92-192 d-55294 bodenheim web: http://www.ichaus.com germany e-mail: sales@ichaus.com appointed local distributors: http://www.ichaus.com/sales_partners p r e l i m i n a r y p r e l i m i n a r y

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